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NCP2830 1W Constant Filterless Class-D Audio Amplifier
NCP2830 is a cost effective mono audio power amplifier designed for portable communication device applications such as mobile phones. Due to its integrated charge pump structure, this part is capable of delivering 1 W of continuous average power to an 8.0 W Bridge Tied Load no matter the voltage provided by a lithium/Ion battery. NCP2830 is a preferred solution for long playback audio with minimum space required. Added to a fast start-up time of 200 ms and a -88dB PSRR, the NCP2830 audio power amplifier is specifically designed to provide high quality and level output power from low supply voltage, requiring very few external components.
Features http://onsemi.com MARKING DIAGRAM
20 1 UQFN20 MU SUFFIX CASE 523AL XXXX ALYWG G
* * * * * * * * * * * * * * * * *
1 W to 8 W load for VDD from 2.7 V up to 5.5 V High quality audio (THD+N = 0.04%) Low noise: SNR up to 100 dB Very Fast Turn On Time: 200 ms Overall system efficiency optimization: up to 89% Superior PSRR (-88 dB): Direct Connection to Battery Very Low Quiescent Current 7 mA Optimized PWM Output Stage: Filterless Capability Selectable gain of 2 V/V or 4 V/V Fully Differential Capability: Thin QFN 3x3 mm, 20 pins This Device uses Halogen-Free Molding Compound This is a Pb-Free Device Cellular Phones and Digital Cameras Personal Digital Assistant and Portable Media Player Audio Accessories GPS
2.2 mF, C3 6.3 V C1P C1 4.7 mF 6.3 V C2 4.7 mF 6.3 V PVDD AVDD C4 C1N C2P 2.2 mF, 6.3 V C2N VB_OUT VB_IN C6 10 mF, 6.3 V C5 10 mF, 6.3 V
XXXX A L Y W G
= Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PGND_D 17
20 INP 1 INM 2 AGND 3 AVDD 4 WM 5 6 SD
19
18
OUTM 16 15 VB_OUT 14 C1P 13 C2P 12 PVDD 11 RES1 10 C1N
VB_IN
Typical Applications
7 GS
OUTP 8 C2N
RES2
9 PGND_CP
Battery + -
Digital Control
WM GS SD 1 mF C7 C8
(TOP VIEW) 20-Pin 3 x 3 x 0.50 mm QFN Exposed pad must be soldered to PCB Ground Plane
NCP2830
INM INP PGND_D PGND_CP AGND RES1 RES2
OUTM OUTP
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.
Audio Inputs
1 mF
Figure 1. Typical Application Circuit
(c) Semiconductor Components Industries, LLC, 2009
August, 2009 - Rev. 0
1
Publication Order Number: NCP2830/D
NCP2830
2.2 mF, 6.3 V 2.2 mF, 6.3 V
PVDD Lithium/ Ion Battery AVDD
C1P
C1N
C2P
C2N
VB_IN VB_OUT
Charge Pump Stepup
2 x 4.7 mF, 0603
2x10 mF, 6.3 V 0603
I/O from Microcontroller
WM
I/O from Microcontroller
GS Shutdown and Biasing SD
I/O from Microcontroller
INM 1 mF Filterless Class D Audio Amplifier INP 1 mF AGND PGND_D RES1 PGND_CP RES2
OUTM
OUTP
Figure 2. Simplified Block Diagram
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NCP2830
PIN FUNCTION DESCRIPTION
Pin 20 3 9 17 4, 12 Pin Name VB_IN AGND PGND_C P PGND_D AVDD PVDD Type I P P P P Description This pin must be externally connection in a star configuration with Pin n15. The Cout filtering (10 mF/6.3 V/0603) capacitor must be connected as close as possible to the connection point. Ground. These pins must be connected separately to the dedicated Ground plane with a minimum of track length. Thus, a star connection is required. Ground. These pins must be connected separately to the dedicated Ground plane with a minimum of track length. Thus, a star connection is required. Ground. These pins must be connected separately to the dedicated Ground plane with a minimum of track length. Thus, a star connection is required.
These pins are dedicated to the signal connection for the battery input. They must be connected to the power source (ie lithium/Ion battery) in a star mode. It must be decoupled by a low ESR ceramic capacitor. (4.7 mF/6.3 V/0603). The use of a 4 or more layers board is advised. In that case, a dedicated plane for this battery voltage is mandatory.
Positive audio input of the fully differential filterless Class D Audio Amplifier Negative audio input of the fully differential filterless Class D Audio Amplifier Negative audio output of the fully differential filterless Class D Audio Amplifier Positive audio output of the fully differential filterless Class D Audio Amplifier Wire Mode pin: When a low level is applied to this pin, the device operates in Normal mode (VB = 5 V typ.). In case of a high level, it switches to a Wire Mode (VB = VDD) Shutdown input. The device enters in shutdown mode when a low level is applied on this pin. Gain Select Input. When a low level is applied to this pin, an internal 2 V/V gain is setup. In case of a high level, it switches to an internal 4 V/V gain. One side of the external charge pump capacitor is connected to this pin, associated with C2P. Using a low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2 mF/6.3 V/0603 recommended). One side of the external charge pump capacitor is connected to this pin, associated with C1P. Using a low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2mF/6.3V/0603 recommended). One side of the external charge pump capacitor is connected to this pin, associated with C2N. Using a low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2 mF/6.3 V/0603 recommended). One side of the external charge pump capacitor is connected to this pin, associated with C1N. Using a low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2 mF/6.3 V/0603 recommended). This pin must be externally connection in a star configuration with Pin n20. The Cout filtering (10 mF/6.3 V/0603) capacitor must be connected as close as possible to the connection point. This VB input is dedicated to supply the internal power stages. Thus, it must be connected to Cout with the lowest impedance connection. Reserved for production. Must be connected to GND plane in final application Reserved for production. Must be connected to GND plane in final application
1 2 16 18 5 6 7 8
INP INM OUTM OUTP WM SD GS C2N
I I
O O I
I I P
10
C1N
P
13
C2P
P
14
C1P
P
15
VB_OUT
O
11 19
RES1 RES2
I I
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NCP2830
MAXIMUM RATINGS
Rating AVDD, PVDD Pins: Power Supply Voltage (Note 2) Digital Input WM; SD; GS Pin: Human Body Model (HBM) ESD Rating are (Note 3) Machine Model (MM) ESD Rating are (Note 3) Latch up Current Maximum Rating QFN 3 x 3 mm Package (Note 7) Thermal Resistance Junction-to-Case Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature (Note 6) Storage Temperature Range Moisture Sensitivity (Note 5) Input Voltage Input Current Symbol VIN VDG IDG ESD HBM ESD MM ILU RqJC TA TJ TJMAX TSTG MSL Value - 0.3 to + 7.0 -0.3 to VDD + 0.3 1 2000 200 (Note 4) 29 (Note 7) -40 to +85 -40 to +125 +150 -65 to +150 Level 1 Unit V V mA V V mA C/W C C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25 C. 2. According to JEDEC standard JESD22-A108B. 3. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) $2.0 kV per JEDEC standard: JESD22-A114 for all pins. Machine Model (MM) $200 V per JEDEC standard: JESD22-A115 for all pins. 4. Latch up Current Maximum Rating: $100 mA for all pins, except digital pins per JEDEC standard: JESD78 class II. $10mA for Digital Pins per JEDEC standard: JESD78 class II 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J-STD-020A. 6. The thermal shutdown set to 150C (typical) avoids irreversible damage on the device due to power dissipation. 7. The RqCA is dependent of the PCB heat dissipation. The maximum power dissipation (PD) is dependent by the min input voltage, the max output current and external components selected. R qCA 125 * T A PD * R qJC
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NCP2830
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between -40C to +85C and TJ up to + 125C for VIN
between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25C and VIN = 3.6 V (Note 8) Symbol GLOBAL SYSTEM VDD ISD ISD IQ IQ IQ RSD RWM RGS VIH VIL FSW1 VB VB VB-Ripple TPrecharge VTR1 VTR2 Operating System Voltage Shutdown Current Shutdown Current Quiescent Current Quiescent Current Quiescent Current Resistance from SD to GND Resistance from WM to GND Resistance from GS to GND Digital Pins High Voltage Digital Pins Low Voltage VSD = low, VGS = Low, VWM = Low VSD = low, VGS = Low, VWM = Low, Vp = 5.5 V (Note 9) 2X Mode, No load 1.5X Mode, No load Wire Mode, No load 2.7 - - - - - - - - 1.2 - - 0.01 - 9.5 7 3 350 350 350 - - 5.5 - 1.5 11 8 4.5 - - - - 0.4 V mA mA mA mA mA kW kW kW V V Parameter Conditions Min Typ Max Unit
BOOST SECTION Charge Pump Switching Frequency Output Regulated Voltage Output Regulated Voltage Output Voltage Ripple Precharge time Transition Voltage between 2X Mode and 1.5X Mode Transition Voltage between 2X Mode and Wire Mode No Load, VINM=VINP=0, VWM= Low, 2X Mode No Load, VINM = VINP = 0, VWM = Low, 1.5X Mode No Load, VINM = VINP = 0, VWM = Low, 2X Mode or 1.5X Mode C5 = C6 = 10 mF 550 4.75 4.75 - - - - 650 5 5 7 1.6 3.8 4.65 750 5.25 5.25 - - - - kHz V V mV ms V V
CLASS D SECTION FSW2 RINL RINH ZSD GHI GLO VOS Tstart TOFF VN VN THD+N THD+N Class D Switching frequency Audio Input resistance Audio Input resistance Shutdown impedance Gain High Gain Low Output Offset Voltage Turn ON time Turn Off time Output Noise Voltage Output Noise Voltage Total harmonic distortion + Noise Total harmonic distortion + Noise No Filter A-Weighting filter Pout = 0.25 W, f = 1 kHz, RL = 8 W Pout = 1 W, f = 1 kHz, RL = 8 W VGS = Low (Note 10) VGS = High (Note 10) VSD = Low VGS = High, RL = 8 W VGS = Low, RL = 8 W VINM = VINP = 0 VB = VDD, VSD = High 275 - - - 1.85 3.7 - - - - - - - 325 15 7.5 20 2 4 1 200 1 56 37 0.04 0.2 375 - - - 2.15 4.3 - - - - - - - kHz kW kW kW V/V V/V mV ms ms mVRMS mVRMS % %
8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at TJ = TA = 25C. 9. The maximum value is measured at 85C 10. Guaranteed by design
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NCP2830
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between -40C to +85C and TJ up to + 125C for VIN
between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25C and VIN = 3.6 V (Note 8) Symbol CLASS D SECTION PSRR CMRR Power Supply Rejection Ratio Common mode rejection ratio Vin = AC Grounded, f = 217 Hz, VWM = VGS = Low, VRIPPLE = 200 mVPP Vic = 1 VPP f = 1 kHz - -88 - dB dB VGS = Low VGS = High VDD = 5 V; Pout = 1 W VDD = 2.7 V; Pout = 0.5 W - - - - 1 -70 -60 89 80 1.2 - - - - - % Parameter Conditions Min Typ Max Unit
h
Efficiency
RL = 8 W
POUT
Output Power
THD+N < 10%, f = 1 kHz, VWM = Low
W
8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at TJ = TA = 25C. 9. The maximum value is measured at 85C 10. Guaranteed by design
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NCP2830
TYPICAL OPERATING CHARACTERISTICS
12 10 8 IQ (mA) 6 4 2 0 2.7 -40C 25C 85C 3.2 3.7 4.2 VDD (V) 4.7 5.2 (nA) 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 2.5
3.0
3.5
4.0 VP (V)
4.5
5.0
5.5
Figure 3. IQ vs VDD
100 90 80 70 60 h (%) 50 40 30 20 10 0 5.5
Figure 4. ISD vs VDD
Pout = 0.25 W 0.5 W 1W 1.5 W 2W
5.0
4.5
4.0 VDD (V)
3.5
3.0
2.5
Figure 5. VB Output Ripple
Figure 6. Boost efficiency vs Output Power
100
100
10 THD (%) THD (%)
VP = 2.7 V
10
VP = 2.7 V
1
3V 3.6 V
1
3V 3.6 V 4.2 V
0.1
4.2 V 4.5 V 5V
0.1
4.5 V 5V
0.01 10
5.5 V
100 Pout (mW)
1000
10000
0.01 10
5.5 V
100 Pout (mW)
1000
10000
Figure 7. THD vs Pout RL = 8 W, WM = Low
Figure 8. THD vs Pout RL = 8 W, WM = High
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NCP2830
TYPICAL OPERATING CHARACTERISTICS
0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 10
PSRR VPP = 200 mVPP -20 RL = 8 W -30 -10 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 -110 10 100
VDD = 2.7 V
PSRR VPP = 200 mVPP RL = 8 W
VDD = 3.3 V
PSRR (dB)
1000 10000 FREQUENCY (Hz)
100000
100
1000
10000
100000
FREQUENCY (Hz)
Figure 9. PSRR vs Frequency
0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 -110 10 100 1000 FREQUENCY (Hz) 10000 100000 PSRR VPP = 200 mVPP RL = 8 W VDD = 3.6 V 0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 -110 10
Figure 10. PSRR vs Frequency
PSRR VPP = 200 mVPP RL = 8 W
VDD = 4.2 V
100
1000 FREQUENCY (Hz)
10000
100000
Figure 11. PSRR vs Frequency
0 -20 -40 RMS VALUE (dB) -60 -80 -100 -120 -140 -160 -180 -200 10
Figure 12. PSRR vs Frequency
100
1000 10000 FREQUENCY (Hz)
100000
Figure 13. Outputs Behavior During GSM Burst
Figure 14. FFT of Switching Signal During GSM Burst
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NCP2830
TYPICAL OPERATING CHARACTERISTICS
7.E-05 6.E-05 5.E-05 NOISE VRMS SNR (dB) 4.E-05 3.E-05 2.E-05 1.E-05 0.E+00 10 VDD = 3.6 V 100 1000 FREQUENCY (Hz) 10000 100000 A Weighting No Filter 120 100 80 60 40 20 0 10 Pout = 1 W VDD = 3.6 V 100 1000 FREQUENCY (Hz) 10000 100000 No Filter A Weighting
Figure 15. Noise vs Frequency
Figure 16. SNR vs Frequency
10 VDD = 3 V WM = High Low Volume 1.0 THD+N (%) Pout = 10 mW 0.1 Pout = 50 mW 0.01 10 100 1000 FREQUENCY (Hz) 10000 100000 THD+N (%)
10
Pout = 250 mW RL = 8 W
VDD = 2.7 V VDD = 3.6 V VDD = 5 V
1.0
0.1
0.01 10
100
1000 FREQUENCY (Hz)
10000
100000
Figure 17. THD+N vs Frequency
Figure 18. THD+N vs Frequency
10
VDD = 3 V VDD = 3.3 V VDD = 3.6 V VDD = 4.2 V VDD = 5 V
0 -10 -20 -30 CMRR (dB) -40 -50 -60 -70 -80 -90
VDD = 2.7 V VDD = 3.6 V VDD = 5 V
Vi = 1 VDD G = 6dB
THD+N (%)
1.0
0.1
0.01 10
100
1000 FREQUENCY (Hz)
10000
100000
-100 10
100
1000 FREQUENCY (Hz)
10000
100000
Figure 19. THD+N vs Frequency
Figure 20. CMRR vs Frequency
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NCP2830
TYPICAL OPERATING CHARACTERISTICS
0 -10 -20 -30 CMRR (dB) -40 -50 -60 -70 -80 -90 -100 10 100 1000 10000 FREQUENCY (Hz) 100000 VDD = 3.6 V 100 90 80 70 60 (%) 50 40 30 20 10 0 0 400 800 1200 Pout (mW)
Vp=2.7V Vp=3V Vp=4.2V Vp=4.5V Vp=5V Vp=5.5V
Vi = 1 VDD G = 12dB
1600
2000
Figure 21. CMRR vs Frequency
Figure 22. Global System Efficiency
VSD
VB
OUTP
Figure 23. Turn ON Sequence
OUTP FILTERED
VB
SD TIED to VDD
IVDD
Figure 24. Turn ON Sequence
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NCP2830
DETAIL OPERATING DESCRIPTION
2.2mF C3 2.2mF C4
0 PGND_CP VB_out
PVDD C1 4.7mF 0
PVDD CHARGE PUMP Mode FSW2 WM SWITCHES MATRIX
VBOUT 0
C6 10mF
VB_in VBIN + - Vref 0 0 C5 10mF 0
WM OUT + -
VB_in
0 Vref FSW1
AVDD C2 4.7mF 0 ANALOG SD AGND 0
FSW2 Mode FSW1 VB_out
GS
15k
OUTM
INM 7.5k 0 INP 7.5k 0 GS 7.5k 7.5k
+ PWM - Modulator 0 VB_out
15k
OUTP
RES2 RES1 PGND_D
0
0
Figure 25. Functional Block Diagram Detailed Descriptions
The NCP2830 consists of two parts: a DC-DC converter and a mono class D amplifier. These two parts are strongly matched in order to obtain the best operation of the global system.
DC-DC CONVERTER
reference. An error amplifier and a voltage to current conversion allow injecting in the Capacitors C3 and C4 the necessary current to maintain 5 V in output. This linear regulation reduces the output voltage ripple (7 mV typ) and allows a noise free operation.
Turn ON/OFF sequence
The DC-DC converter is based on a charge pump technique. The switching frequency is synchronized with the class D amplifier (FSW2 = 2 x FSW1) in order to avoid mixing frequency. The regulation is based on a voltage regulation. The output voltage is permanently monitored through a resistor ladder and compared to an internal
The turn ON and turn OFF sequence has been adapted to an audio applications environment. When the battery voltage is connected to the VDD pins, the output capacitance is precharged to the VDD voltage. When VSD is High, the charge pump is activated and the output voltage rises up to
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NCP2830
5 V. Internally, the class D amplifier starts to operate when VB equals 4.5 V. When VSD is low, the charge pump is deactivated and the VB voltage is maintain to the VDD value. During this shutdown mode, it is not possible to sink current through the VB pin. Figure 26 depicts the turn ON/OFF sequence.
OUTP OUTM Audio
30 kHz Built-in Low Pass Filter
This filter allows directly connecting a DAC or a CODEC to the NCP2830 input without risk of output noise increase due to a mixing frequency with the DAC/CODEC output frequency. Consequently, the best operation with DACs or CODECs is guarantee without need of additional external components. Due to its fully differential architecture the NCP2830 does not require input capacitors if the differential source is biased from 0.5 V to VDD - 0.8 V. However, it is possible to use input capacitors when the differential source is not biased or in single ended configuration. In this case it is necessary to take into account the corner frequency which can influence the low frequency response of the NCP2830. The following equation will help to choose the adequate input capacitors.
fC + 1 2p @ Z in @ C in
(eq. 1)
Input Capacitors Cin
VDD
VDD 0
SD 0 5V 4.5 V VDD VD 0 TPrecharge Tstart Toff 0.9 x VDD
Figure 26. Turn ON/OFF Sequence
With Zin the input impedance of the NCP2830.
Overcurrent Protection
In order to maximize the global efficiency, the system permanently monitors the battery voltage and changes its operating mode: * When VDD is less than 3.8 V (typ) the system operates in 2X mode. * Between 3.8 V and 4.65 V the system operates in 1.5X mode. * If VDD is greater than 4.65 V the system switches automatically to Wire Mode operation (VB = VDD)
WM pin
This protection allows detecting an over current in the H-Bridge. When the current is higher than 2 A the H-Bridge is put in high impedance. When the short circuit is removed or the current is lower, the NCP2830 go back to normal operation. This protection allows avoiding overcurrent due to a bad assembly (Output shorted together, to VB or to ground).
DESIGN PROCEDURE Components Selection
This external pin allows controlling the activation of the boost whatever the battery voltage is. For example, if no power is required, there is no need to boost the supply voltage of the class D amplifier. In that case, disabling the boost by a high logic on WM pin, allows supplying directly the class D by the battery voltage (VB = VDD) and optimizing the efficiency.
CLASS D AMPLIFIER
Use very low ESR ceramic capacitors (X5R/X7R) will help to reduce the output resistance of the charge pump and thus improve the system efficiency.
Input Capacitor (C1 and C2)
The NCP2830 is based on a mono class D audio amplifier. This structure is composed by a preamplifier stage, a PWM stage and a H-Bridge stage.
Gain selection
NCP2830 is aimed to be connected on the battery line. For such a device, it is mandatory to get as low ripple as possible so as to avoid conducted emission on the battery line. As stated above, the noise generated by turn-on and turn-off transients is optimized by a controlled switching speed. Placing two 4.7 mF/6.3 V (0603 size) input capacitors as close as possible to PDD and AVDD pin will also help to avoid any disturbance for other sensitive parts also connected on the battery line.
Flying Capacitors (C3 and C4)
The preamplifier stage consists in applying a gain to the input signal selectable by a dedicated digital pin GS. The gain setting is given by the following truth table:
GS 0 1 Gain Av V/V 2 4 Input Impedance kW 15 7.5
As stated above, the value of these capacitors has a direct impact on the load regulation and output resistance of the charge pump. The converter must provide a regulated DC voltage with a sine wave AC current, the frequency of which is twice the audio signal frequency. Selecting a 2.2 mF/6.3 V (0603 size) will help regarding the load regulation and the device's ability to provide sufficient current drive.
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NCP2830
Output Capacitors (C5 and C6) Optional Output Filters
The value and ESR of this capacitor are directly linked to the ripple of the regulated output voltage. As the charge pump must provide up to 450 mA to the internal audio amplifier, two 10 mF/6.3 V capacitors (0603 size) should allow the converter to give its maximum output power capability.
Layout Recommendations
If the traces between the amplifier and the speaker are short, there's no need for an output filter. In case of applications where short output traces are not possible, it is necessary to protect the application as much as possible from EMI pollution. The use of small 0603 Chip Ferrite beads is a good alternative.
As all switching devices, special care must be observed in routing power supplies and ground. VDD pins must be decoupled by C1 and C2 placed as close as possible to the NCP2830 in order to reduce parasitic inductance. GND pins must be connected to a ground plane. In order to reduce parasitic elements, it is better to connect all the ground pins to the same Ground plane.
Figure 28. Optional EMI Filter Thermal Considerations
For thermal dissipation, it is recommended to connect the exposed pad of the NCP2830 to a plan connected to the ground as depicted Figure 27.
Demo Board Available:
The NCP2830EVB/D evaluation board that configures the device in typical application.
Figure 27. Recommended PCB Layout
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NCP2830
TYPICAL APPLICATION
C3 2.2 mF, 6.3 V C4 2.2 mF, 6.3 V
Battery + - C1 4.7 mF 6.3 V C2 4.7 mF 6.3 V PVDD AVDD
C1P
C1N
C2P
C2N VB_OUT VB_IN C5 10 mF, 6.3 V 10 mF, 6.3 V C6
WM Digital Control GS SD
NCP2830
INM Audio Inputs INP AGND PGND_D RES1 PGND_CP RES2
OUTM
OUTP
Figure 29. Fully Differential Configuration
C3
2.2 mF, 6.3 V
C4
2.2 mF, 6.3 V
Battery + - C1 4.7 mF 6.3 V C2 4.7 mF 6.3 V PVDD AVDD
C1P
C1N
C2P
C2N VB_OUT VB_IN C5 10 mF, 6.3 V
10 mF, 6.3 V C6
WM Digital Control GS SD
NCP2830
1 mF Audio Inputs
C7
INM
OUTM
1 mF
C8
INP AGND PGND_D RES1 PGND_CP RES2
OUTP
Figure 30. Single-Ended Configuration ORDERING INFORMATION
Device NCP2830MUTXG Package UQFN20 3x3 mm (Pb-Free) Shipping 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCP2830
PACKAGE DIMENSIONS
UQFN20 3x3, 0.4P CASE 523AL-01 ISSUE O
D
PIN ONE REFERENCE
AB L1 E
L
L
DETAIL A
ALTERNATE TERMINAL CONSTRUCTIONS
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e L L1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 3.00 BSC 1.70 1.90 3.00 BSC 1.70 1.90 0.40 BSC 0.20 0.40 0.00 0.15
2X 2X
0.15 C
0.15 C 0.10 C 0.08 C
TOP VIEW
DETAIL B
A3 A
A1
ALTERNATE CONSTRUCTIONS
DETAIL B
NOTE 4
A1 SIDE VIEW C
SEATING PLANE
SOLDERING FOOTPRINT*
0.52 1
20X
DETAIL A 6
D2
11
E2
1 16 20X
2X
3.30
20X
L
e
b 0.10 C A 0.05 C
B
BOTTOM VIEW
NOTE 3
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
http://onsemi.com
15
CC EE EE
0.40 PITCH
EE EE EE
III III III
EXPOSED Cu
MOLD CMPD
A3
2X
1.86
0.26
DIMENSIONS: MILLIMETERS
20X
NCP2830/D

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